Phase-locked loops (PLLs) and delay-locked loops (DLLs) may be used to perform tasks such as de-skewing clock signals, recovering clock signals, synthesizing clock frequencies, and implementing clock distribution networks. PLLs typically employ a variable-frequency circuit such as a voltage-controlled oscillator (VCO) to lock an output signal to a reference signal, while DLLs typically employ a variable-delay circuit such as a voltage-controlled delay line to lock an output signal to an input signal.
More specifically, a PLL typically includes a phase detector and a voltage-controlled oscillator (VCO). The VCO, which includes an input to receive a control voltage and an output to generate an oscillation output signal, adjusts the frequency of the oscillation output signal in response to the control voltage. The control voltage, which is generated by the phase detector and other loop components (such as a charge pump and a filter), settles to a value that makes the VCO oscillate at the desired frequency. Additionally, the phase error at the output of the phase detector approaches zero. Thus, during operation, the loop adjusts the control voltage such that, in steady state, the VCO oscillates at the desirable frequency and the phase of the output clock has a specific relation with the phase of the reference clock.
A DLL typically includes a phase detector and a voltage-controlled delay line. The loop adjusts the control voltage such that the delay line provides a desired delay (and the phase error at the output of the phase detector is zero). The voltage-controlled delay line, which has inputs to receive the control voltage and the input signal, selectively delays the output signal until the output signal is delay-locked with the input signal. DLLs may be desirable over PLLs for multiplying a clock frequency by an integer value because, for example, DLLs typically provide more stability, employ smaller loop filters, and exhibit lower phase noise than PLLs.
FIG. 1 shows a conventional DLL circuit 100 that delay locks an output clock signal CLK_OUT with an input clock signal CLK_IN. More specifically, DLL circuit 100 includes a phase and frequency detector (PFD) 110, a charge pump 120, a loop filter 130, and a voltage-controlled delay line 140. A crystal oscillator may generate the oscillating clock signal CLK_IN to first inputs of the PFD 110 and the delay line 140. PFD 110 compares the phase of CLK_IN and a feedback signal CLK_FB to generate up (UP) and down (DN) control signals that are converted to a charge (QC) proportional to the phase difference of the two clocks by charge pump 120. The charge generated by the charge pump is filtered (e.g., integrated) by filter 130 and provided as a control voltage VC to delay line 140. The delay line 140, which includes a number (n) of series-connected delay elements 141 that provide a corresponding number of delay taps T1-Tn, selectively delays CLK_IN in response to VC to generate CLK_OUT. In this manner, the output signal CLK_OUT, which is provided as the feedback signal CLK_FB to PFD 110, may be synchronized (e.g., delay-locked) with the input signal CLK_IN by adjusting the signal delay within delay line 140 until the period of CLK_OUT equals the period of CLK_IN.
The delay taps T1-Tn provide a plurality of phase delays (e.g., φ1, φ2, . . . φn) of the clock signal. As such, the DLL 100 of FIG. 1 may be used as a frequency synthesizer by performing logic operations on the multiple clock phases at taps T1-Tn to achieve frequency multiplication of the input signal CLK_IN. Unfortunately, performing logic operations on the multiple clock phases provided by taps T1-Tn may introduce unwanted delays, which in turn may undesirably generate spurs in the output clock signal. Another disadvantage of DLL 100 being used as a frequency multiplier is that programmability of the multiplying factor is difficult to implement.
Accordingly, there is a need to provide a frequency multiplying DLL that can multiply a reference frequency by an arbitrary integer value while minimizing noise and spurs in the output clock signal.